DFS Issue 2 Version Information

G4HUP F-DFS Issue 2 Version 66.667MHz

This F-DFS version is primarily intended for reference frequency locking of SDR-IQ and SDR-14 receivers.

Configuration Document download here

Bill of Materials download here

PCB Preparation

Error issue see Errata. You need to correct item 1

PCB must have the following modifications carried out during assembly:

If using S18 inductors, prepare shielding for both of the VHF BPF's - for L205/206, use a piece of hobby brass 67mm x 17mm. Fold each end in at 17.5mm. Cut a screen to fit centrally between the two coils. For L601/602, the procedure is identical - but the screen is 61mm long before bending.

Circuit Realisation

The 66.667MHz version requires:

the input buffer (may be omitted if 10MHz source has at least +10dBm available)
the diode multiplier (Sheet 2),
Logic Stages with 1 divider (IC402) - both inverter packages (IC401/404) are required (Sheet 4)
3.33MHz low pass filter, (Sheet 9)
no diplexer is used in this version

The input buffer circuit (Sheet 1) can also be used to provide a 'daisy-chain' 10MHz output with this implementation.

Divider Programming

Divider 1 (IC402) must be set to divide by 3 to give 3.33MHz output - hence the jumpers must be programmed as binary 13 (1101) reading in order DCBA. Jumper B (pin 4, SJ2) must be grounded, the remaining 3 taken to the 10k pull-up resistor, R403

Divider Output: Divider 1 output is taken from pin 14 (SJ5).

Mixer Choices

Standard ADE-1 mixer required for M601.

Once the 3.3MHz output has been checked, you will need to jumper across from the output of the attenuator (R904/5) to the input of the mixer M601.

Alignment

Tune each filter onto frequency using a signal generator and power meter or spectrum analyser as you go through the construction. This will ease the final tune up. As you complete each chain, adjust it before the mixer is inserted.

For example, build the 70MHz filter, F1, align it, then build the amplifier stages following. Check and re-align. Build the diode multiplier and test through to output of the amplifiers. Set the attenuator value to 7dB to give approx +6dBm into the mixer. Build the logic stages and check the output is correct in frequency. Using a scope, check that there is a nice square wave output from IC401, pin 2 (may be easier to look at IC402 pin2) An attenuator of 10dB is needed on the 3.3MHz signal to the mixer.

Insert the mixer M601 and check the output through the 66.7MHz BPF, F8, optimising if necessary. Follow through with the remaining filters.

Final alignment should be done on a spectrum analyser. Carefully adjust the trimmer capacitors of the crystal filter for minimum spurii, and maximum wanted signal. The adjustments are iterative, and very small movements make significant differences to the output. You may also find it beneficial to make minor adjustments to the 70MHz filters to get the best symmetry and rejection of other products.

Page created 7 Jun 2009

Page last updated 23 Aug 2010